Ferroelectric memory devices can have nonvolatile characteristics such that the device retains data even when power is not supplied to the device. Like other memory devices, such as DRAMs and SRAMs, ferroelectric memory devices may operate at low voltages. Accordingly, ferroelectric memory devices can be used in devices commonly referred to as “smart cards” or the like.
Typical methods of fabricating ferroelectric capacitors in ferroelectric memory devices can include forming a thick lower conductive layer on a semiconductor substrate and patterning the lower conductive layer to form a lower electrode of the capacitor. A ferroelectric material can be formed on the lower electrode using, for example, a sol-gel, Chemical Vapor Deposition (CVD) or sputtering technique. The ferroelectric layer can then be patterned.
An upper conductive layer can be formed on the patterned ferroelectric layer. The upper conductive layer can also be patterned to provide an upper electrode for the ferroelectric capacitor. As a result, conventional ferroelectric capacitors can exhibit planar-type structures. The lower and upper conductive layers are typically formed using a Noble metal such as iridium or platinum. The lower conductive layer can also include a Noble metal oxide material.
In some conventional planar-type ferroelectric capacitors, the thickness of the lower electrode is used to provide increased surface area which can increase the capacitance thereof. However, it may be difficult to pattern the thick lower conductive layer due to limitations in etching the Noble metal used. Also, the additional photolithography steps used to form the lower electrode can cause the upper electrode to be misaligned to the underlying conductive material used to form the lower electrode.
It is known to fabricate cylindrically shaped bottom electrodes to increase the surface area of the bottom electrode without using an etching process. In some conventional processes, an insulating layer is formed on a semiconductor substrate and is patterned to form an opening therein that exposes a portion of the substrate. A Noble metal layer can be conformally deposited over the resultant structure and in the opening. A sacrificial insulating layer can be formed thereon including in the opening. The Noble metal layer is planarized using a Chemical-Mechanical Polishing (CMP) technique until the surface of the sacrificial insulating layer is exposed, thereby forming a U-shaped bottom electrode in the opening. The CMP technique is used to electrically separate adjacent U-shaped bottom electrodes.
However, there may also be limitations of the CMP technique in patterning the Noble metal layer in that misalignment to an underlying conductive material may occur because an additional photolithography step is used to form the U-shaped bottom electrode.
FIG. 1 illustrates a cross-sectional view of a lower plug formed using conventional methods. Referring to FIG. 1, a lower insulating layer 3 is formed on a semiconductor substrate 1. The lower insulating layer 3 is patterned using conventional photolithography to form contact recesses that expose the substrate 1. Each of the contact recesses is filled with a first contact plug 5. A sacrificial insulating layer 6 is formed on the surface of the lower insulating layer 3 including the first contact plugs 5.
FIG. 2 illustrates a cross-sectional view of an upper plug formed using conventional methods. Referring to FIG. 2, in subsequent steps, the sacrificial insulating layer 6 is patterned, using conventional photolithography, to form openings 7 that expose the first contact plugs 5. The widths of the openings 7 are greater than the widths of the first contact plugs 5 to reduce misalignment between the first contact plugs 5 and the openings 7. Each of the openings 7 is filled with a second contact plug 9 which can be the same or similar to the conductive material used to form the first contact plugs 5. Accordingly, the first and second plugs are formed in separate steps. As a result, the widths of the second contact plugs 9 are larger than that of the first contact plugs 5. Unfortunately, this type of 2-step photolithography can be complicated to implement and may contribute to misalignment of the first and second plugs.
FIG. 3 illustrates a cross-sectional view of a ferroelectric capacitor formed on the upper and lower plugs formed using conventional methods. Referring to FIG. 3, the sacrificial insulating layer 6 is selectively removed to expose the side walls of the second contact plug 9 which increases the exposed surface area of the second contact plug 9. A first Noble metal layer 11, a ferroelectric layer 13, and a second Noble metal layer 15 are sequentially formed on the entire surface of the resultant structure where the sacrificial insulating layer 6 was removed. The second Noble metal layer 15, the ferroelectric layer 13, and the first Noble metal layer 11 are sequentially patterned to form a plurality of ferroelectric capacitors, which are spaced-apart from one another on the substrate 1.
Unfortunately, as the cross-sectional width of the second contact plug 9 increases, it may be difficult to completely separate adjacent ferroelectric capacitors from one another since the spacing 17 that separates adjacent ferroelectric capacitors is reduced as a result of the increased width of the second contact plug 9. Furthermore, the difficulty in separating the adjacent ferroelectric capacitors can be worsened because it may be difficult to pattern electrodes made from Noble metals.